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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT TYPE FUNCTION
DC-AC Inverter Control IC
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20V High voltage process 1ch control with Full-Bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin Automatic Judge function for External synchronization of lamp oscillation BURST mode controlled by PWM and DC input
Absolute Maximum Ratings
Parameter Supply Voltage
REG PIN
Symbol
VCC VREG Topr Tstg Tjmax
Limits
20 15 -40+85 -55+150 +150
2
Unit
V V mW
Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation
*1 *2
Pd
1024(BD9217FV) 688(BD9217F)
Pd derate at 8.2mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm) Pd derate at 5.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition
Parameter Supply voltage oscillation frequency BCT oscillation frequency Symbol
VCC FOUT FBCT
Limits
7.5 19.5 30 90 0.05 1.00
Unit
V kHz kHz
REV. C
2/4 Electric
CharacteristicsTa=25VCC=12V Limits Parameter Symbol MIN. TYP. MAX. Unit Conditions
WHOLE DEVICE Operating current Stand-by current STAND BY CONTROL Stand-by voltage H Stand-by voltage L UVLO BLOCK Operating voltage (VCC) Hesteresis width (VCC) Operating voltage (UVLO) Hesteresis width (UVLO) REG BLOCK REG output voltage REG source current SOFT START BLOCK Soft start current SS_COMP detect voltage OSC BLOCK RT Output Voltage STR ON Resistor value BOSC BLOCK BOSC Max voltage BOSC Min voltage BOSC constant current BOSC frequency FEED BACK BLOCK IS threshold voltage VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage OUTPUT BLOCK N output sink resistance N output source resistance P output sink resistance P output source resistance Drive output frequency MAX DUTY OFF period CT SYNCHRONOUS BLOCK Input High voltage range Input Low voltage range FAIL BLOCK FAIL High voltage FAIL Low voltage SEL BLOCK Input High voltage range Input Low voltage range TIMER LATCH BLOCK VCP ICP 1.91 0.85 2.00 1.05 2.09 1.25 V uA VSEL_H VSEL_L 5.0 -0.3 15 0.3 V V VFAIL_H VFAIL_L 2.95 -0.3 3.1 3.25 0.3 V V VCT_CLKIN_H VCT_CLKIN_L 2.5 -0.3 5.0 0.5 V V Rsink_N Rsource_N Rsink_P Rsource_P Fout MAX DUTY TOFF 1.8 4.5 1.8 4.5 57.9 100 3.5 9.0 3.5 9.0 60.0 48.0 200 7.0 18.0 7.0 18.0 62.1 400 kHz % ns RT=28.5k, FB=0V FOUT=60kHz Vis Vvs Iis1 Iis2 Ivs VISCOMP 1.225 1.220 40 0.64 1.250 1.250 50 0.66 1.275 1.280 0.9 60 0.9 0.68 V V uA uA uA V DUTY=2.0V DUTY=0V, IS=1.0V VBCTH VBCTL IBCT FBCT 1.94 0.40 1.35/BRT 291 2.00 0.50 1.50/BRT 300 2.06 0.60 1.65/BRT 309 V V A Hz (BRT=36.2K, BCT=0.047uF) fBCT=0.3kHz fBCT=0.3kHz VRT RSRT 1.05 1.50 100 1.95 200 V Iss VSS 1.5 2.3 2.0 2.5 2.5 2.7 uA V VREG IREG 7.35 20 7.50 7.65 V mA VCC > 8.5V Source current VstH VstL 2.0 0.3 VCC 0.8 V V System ON System OFF Icc1 Icc2 8.0 10 16 30 mA uA FOUT=60kHz, FB=GND
Vuvlo Vuvlo Vvlo_u Vvlo_u
6.65 0.37 2.4 0.075
7.00 0.50 2.5 0.100
7.35 0.63 2.6 0.125
V V V V
CP timer latch detect voltage CP timer latch charge current COMP BLOCK COMP over voltage detect voltage Hysteresis width COMP
VCOMP Vcomp
3.88 0.138
4.00 0.185
4.12 0.232
V V
VSS > 2.4V
(This product is not designed to be radiation-resistant.)
REV. C
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Package Dimensions DEVICE MARK
BD9217F
BD9217FV
Lot No.
SOP24(unit:mm)
SSOP-B24(unit:mm)
Block Diagram
VCC REG SEL CLKIN RT BRT BCT DUTY
REG BLOCK
OSC BLOCK
BOSC BLOCK
DUTY BLOCK
STB
STB BLOCK
SYSTEMON/OFF REG
SS FB OUTPUT BLOCK P1 N1 IS VS F/B BLOCK PWM BLOCK LOGIC BLOCK P2 N2
SS CT
PGND
PROTECT BLOCK GND UVLO
VCC
COMP
CP
SRT
UVLO
FAIL
Pin Description
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 PIN NAME
PGND N2 P2 UVLO CLKIN RT SRT GND BCT BRT DUTY STB
FUNCTION
Power Ground for FET drivers NMOS FET driver (Channel 2 side) PMOS FET driver (Channel 2 side) Input of Under Voltage Lock Out CT Synchronous signal input External resistor between RT and GND for adjustment frequency of saw tooth wave External resistor between SRT and RT for adjustment frequency of kick-off Ground External capacitor between BCT and GND for adjusting the BURST triangle oscillator External resistor between BRT and GND for adjustment frequency of Burst dimming Control Burst-dimming by PWM signal or DC Stand-by switch
PIN No. 13 14 15 16 17 18 19 20 21 22 23 24
PIN NAME
CP FAIL SEL VS IS FB SS REG COMP VCC
FUNCTION
External capacitor between CP and GND for timer latch Error Indication output pin Normal : H, Error : L Selector pin for external syncro-mode frequency REG(Pin 20) : Pull-up fin=Fout(DUTY=50%), Gnd-short : fin=Fout x 2 Error amplifier input 1 Error amplifier input 2 Error amplifier output External capacitor between SS and GND for Soft Start Control and detect the time of Soft Start regulator output Input of over voltage detector Power supply input with UVLO Protection PMOS FET driver (Channel 1 side) NMOS FET driver (Channel 1 side)
P1 N1
REV. C
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NOTE FOR USE
When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. . The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. . Mounting failures, such as misdirection or miscounts, may harm the device. . A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin. . If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual current flow into pins may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection diodes for prevention against backward current flow. . BD9217F/BD9217FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. . Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. . About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. . By STB voltage, BD9217FV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8 2.0V). . The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig.1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. .
Resistance (PinA) (PinB) C
Transistor (NPN) B E GND
N
P
P N
P P substrate GND Parasitic diode (PinB)
P substrate GND Parasitic diode
N
N
(PinA) B Parasitic diode GND
C E GND
Other adjacent components Parasitic diode
Fig.1 Simplified structure of a Bipolar IC
REV. C
Notice
Notes
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